1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that operates in a high-speed test mode at a higher frequency than an external clock frequency and further relates to a method for generating an internal clock for a semiconductor memory device.
2. Description of the Related Art
As the operating speed of semiconductor memory devices continues to increase, there is an increased likelihood that the operation speed of a tester for testing the semiconductor memory device will unfortunately fail to keep up with the operating speed of the semiconductor memory device.
For example, while the semiconductor memory device can operate at a frequency of about 400 MHz, a tester may not be able to generate signals greater than about 200 MHz. In this case, when the tester is used to test the semiconductor memory device at a frequency of 200 MHz, more time is required to complete the test. Particularly, when the semiconductor memory device operates at a high speed, the test cannot be properly performed by the tester having such a low operating speed.
There may be instances where a high-speed semiconductor memory device, such as a dynamic random access memory (DRAM), is to undergo testing using a low-speed tester with a low operating speed, that is, where a high-speed test mode needs to be performed using the low-speed tester. In this case, an internal clock of a frequency higher than that of an external clock applied from the low-speed tester may be generated in the high-speed semiconductor memory device so as to make it possible to test the high-speed operation of the high-speed semiconductor memory device using the low-speed tester. For example, a doubled clock having a doubled frequency with respect to the external clock frequency may be generated by performing an XOR operation of the external clock and a 90°-delayed external clock, thereby making it possible to test the high-speed semiconductor memory device at high speed.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes a delay-locked loop (DLL) circuit 110, a clock buffer 120, and an internal circuit 130.
In a normal mode operation, the DLL circuit 110 generates, by causing an external clock CLK to pass through a DLL, a data clock for outputting data DATA read from a memory cell array to an external device. In the normal mode of operation, the data clock is generated so that the data can be output in synchronization with the external clock CLK. In a high-speed test mode, the DLL circuit 110 generates a doubled clock with a frequency higher than that of the external clock CLK by using the external clock CLK and a 90°-delayed external clock CLKB, and generates the data clock for outputting the read data DATA from the memory cell array to the external device by causing the external clock CLK to pass through the DLL.
In the normal mode operation, the clock buffer 120 buffers the external clock to generate an internal clock INT_CLK. In the high-speed test mode, the clock buffer 120 performs an XOR operation of the external clock CLK and the 90°-delayed external clock CLKB to generate the internal clock INT_CLK having a frequency that is double that of the external clock CLK.
The internal circuit 130 includes a test mode circuit 131 and a peripheral circuit 132. The internal circuit 130 performs a read/write operation of the semiconductor memory device in response to the internal clock INT_CLK.
The test mode circuit 131 controls various test mode settings of the semiconductor memory device. The test mode circuit 131 includes a test mode register, and outputs a test mode signal TEST_MRS according to a test mode set by a test mode command received from an external source.
The peripheral circuit 132 denotes all circuits of the internal circuit 130 except the circuits related to the test mode setting. For example, the peripheral circuit 132 includes a memory cell array, a row decoder, a column decoder, and a sense amplifier. The peripheral circuit 132 operates according to the test mode signal TEST_MRS received from the test mode circuit 131. For example, in one test, the peripheral circuit 132 reads data from the memory cell array and outputs the read data.
As illustrated in FIG. 1, when the same internal clock INT_CLK is input into the test mode circuit 131 and the peripheral circuit 132, a clock of a frequency higher than that of the external clock CLK is also applied to the test mode circuit 131 in the high-speed test mode. Since the test mode circuit 131 needs to process various test commands according to the external clock CLK, it may not properly process a test command from an external source when a high-speed clock is internally applied in the high-speed test mode.
FIG. 2 is a block diagram of the DLL circuit 110 illustrated in FIG. 1.
Referring to FIG. 2, the DLL circuit 110 includes a clock doubler 210, a buffer 220, a selector 230, a DLL 240, a buffer 250, and an output driver 260.
The clock doubler 210 generates a doubled clock 2×CLK with double the frequency of the external clock CLK by using the external clock CLK and the 90°-delayed external clock CLKB. As illustrated in FIG. 2, the clock doubler 210 may be an XOR gate.
The buffer 220 buffers the external clock CLK.
The selector 230 selects an output signal of the buffer 220 or an output signal of the clock doubler 210 in response to a high-speed test mode signal HSC. That is, the selector 230 outputs the external clock from the buffer 220 in the normal mode, and outputs the doubled clock 2×CLK from the clock doubler 210 in the high-speed test mode. The selector 230 may be implemented using a multiplexer (MUX).
The DLL 240 includes a variable delay line (VDL) 241, a delay compensator 242, a phase detector (PD) 243, and a low-pass filter (LPF) 244.
The VDL 241 delays an output signal of the selector 230. An output signal of the VDL 241 is output through the buffer 250 as a data clock CLKDQ.
The delay compensator 242 compensates the output signal of the VDL 241 for a delay of the VDL 241. For example, the delay compensator 242 delays the output signal of the VDL 241 to compensate for the delay of the VDL 241.
The PD 243 detects a phase difference between the output signal of the selector 230 and an output signal of the delay compensator 242.
The LPF 244 low-pass filters an output signal of the PD 243 to output a signal for adjusting the delay of the VDL 241.
The output driver 260 outputs the read data DATA from the memory cell to an external device according to the data clock CLKDQ. Generally, in the normal mode operation, the output driver 260 drives the read data DATA to be output in synchronization with the external clock CLK.
FIG. 3 is a block diagram of the clock buffer 120 illustrated in FIG. 1.
Referring to FIG. 3, the clock buffer 120 includes a clock doubler 310, a buffer 320, and a selector 330.
The clock doubler 310 generates a doubled clock having a frequency that is double the frequency of the external clock CLK by using the external clock CLK and the 90°-delayed external clock CLKB.
The buffer 320 buffers the external clock CLK.
The selector 330 selects an output signal of the buffer 320 or an output signal of the clock doubler 310 in response to a state of a high-speed test mode signal HSC. That is, the selector 330 outputs the external clock from the buffer 320 as the internal clock INT_CLK when operating in the normal mode, and outputs the doubled clock from the clock doubler 310 as the internal clock INT_CLK when operating in the high-speed test mode.
FIG. 4 is a timing diagram illustrating a problem associated with the conventional internal clock generation method.
Referring to FIG. 4, the internal clock INT_CLK in the normal mode is generated by buffering the external clock CLK, and the internal clock INT_CLK in the high-speed test mode is generated by performing an XOR operation of the external clock CLK and the 90°-delayed external clock CLKB. When compared to the internal clock INT_CLK in the normal mode, the internal clock INT_CLK in the high-speed test mode has an XOR delay, that is, a delay due to the XOR operation.
The XOR delay is commonly generated at the DLL circuit 110 and the clock buffer 120. Particularly, the XOR delay of the DLL 240 causes a delay of the data clock CLKDQ illustrated in FIG. 4. The delay of the data clock CLKDQ in turn causes the output data DOUT of the output driver 260 to be more delayed than the external clock CLK by a delay time tDQSCK.
Furthermore, a process variation (PVT variation) corresponding to the XOR delay is generated to reduce a valid data window tDV of the output data DOUT. This XOR delay causes a difference between the operating characteristics of the semiconductor memory device in the normal mode and in the high-speed test mode, thereby preventing a proper test operation on the semiconductor memory device.
In order to solve the problem due to the above XOR delay, the delay compensator 242 compensates for the XOR delay as well as the delay of the VDL 241. When the delay compensator 242 also compensates for the XOR delay, the data clock CLKDQ can be generated such that the output data DOUT from the semiconductor memory device is synchronized with the external clock CLK. However, the margin between the internal clock INT_CLK and the data clock CLKDQ in the high-speed test mode is undesirably reduced, thereby reducing the frequency margin of the semiconductor memory device.